The pseudo-random generator

 

What is a pseudo-random generator?    Why can it be useful?

A pseudo-random generator produces a succession of logical zeros and ones. It is known as random because this succession is arbitrary. However, when the sequence arrives in its term, the generator does not stop. The already transmitted sequence is again reproduced. From where the qualifier of pseudo-random.

Example:     1 1 1 0 0 1 0     1 1 1 0 0 1 0     1 1 1 0 0 1 0     1 1 1 0 0 1 0     1 1 1 0 0 1 0     

The elementary sequence presented above is short: it has a length of 7 bits. We will see later we can easily create much longer sequences.

The pseudo-random generator plays in data transmission the same role as a pattern generator in television. Indeed, even if the sequence produced by a pseudo-random generator appears arbitrary, it is not really true. We can know the sequence because it is by perfectly definite by construction and wiring. Specific measuring tools can recognize standardized sequences and display the error rate in transmission.
The transmitted signal presents a very broad and spread spectrum which resembles a noise. The transmission impairments of the signal can be highlighted, in particular by means of the eye pattern.

 

Of what is made up a pseudo-random generator?

It utilizes two types of components: " the shift register " and " the exclusive-or gate "

- "the shift register" :

On the positive-going edge of the clock pulse, the logical level which was present on the input is transferred on the output.

- "the exclusive-or gate" :

It has two inputs and one output. So that the output is at the logical level " 1 ", it is necessary that the level on one of the two inputs is equal to " 1 ".
But attention, there is a special case: if the two inputs are at the logical level " 1 ", the output gives a logical level " 0 ".

 

 

Schematic diagram and operation of a pseudo-random generator:

example of a generator with three registers:

 

Let us take for assumption the following starting situation: Out_1 = 1, Out_2 = 1, Out_3 = 1, then In_1 is equal to " 1 " (exclusive-or)

The table describing the situation after each positive-going edge of the clock signal is the following:

step	Out_1	Out_2	Out_3	In_1
0	1	1	1	0
1	0	1	1	0
2	0	0	1	1
3	1	0	0	0
4	0	1	0	1
5	1	0	1	1
6	1	1	0	1
7	1	1	1	0
8	0	1	1	0
9	0	0	1	1

 

The situation at step 7 is identical to that of departure. The pattern will thus reproduce.

The sequence generated by this device is thus (Out_3 output): 1 1 1 0 0 1 0

 

Note: the situation Out_1 = 0, Out_2 = 0, Out_3 = 0 is prohibited and led to a blocking of the generator. There are several manners to avoid the blocking :

- positioning of the registers forced to starting by RC circuits

- detection of the combination prohibited by means of a or gate and then inversion of the input In_1

- installation of a modulo N counter, incremented to each zero at the output and reseted at zero for each one. Its overflow means that it there has blocking and causes the insertion of a one on the input In_1.

 

The pseudo-random generator we use:

The generator with three registers presented previously was useful to illustrate the principle of operation. The length of the generated elementary sequence is a function of the number of shift registers employed. With the 3 registers of the example above we had only one sequence of 7 binary bits, with 15 registers we can obtain a sequence of 32767 bits and with 20 registers 1048575 bits. When it is known that a simple DIL 14 package can contain 8 registers.....

We may find benefits to respect the large standards of the field. For the 2 Mbit/s data signaling, the ITU recommendation O.150 a pseudo-random generator with 15 registers, fourteenth and fifteenth outputs being connected on the inputs of an exclusive-or, the output of this gate being connected to the input of the first register.

The schematic diagram is the following:

 

The electronic achievement of this device is detailed in the heading "schematics".

B5+ et 73 de Jean-François Fourcadier, F4DAY

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